This invention relates to a demultiplexer for originally synchronous digital signals which are internested word-wise, with m words per smallest frame and n bits per word, and containing a shift register at the input end.
In digital time division multiplexers processes in which primary signals which are synchronous to one another are internested word-wise and additional signals which are to be additionally transmitted are inserted, the information bits of a primary signal are non-uniformly distributed in the multiplex signal to a marked degree. Therefore, the restoration of a uniform primary signal in the demultiplexer at the receiving end requires extensive intermediate stores which compensate the non-uniform distribution of the information bits.
German published patent application 2 336 286 discloses such a demultiplexer which consists of m shift registers, m stores and m parallel-series converters.
A positive stuffing process has been recommended which combines four 2048 kbit/s signals to form one 8448 kbit/s signal. A process variant provides that four synchronous primary signals are internested bit-wise. In addition word-wise internesting for example for a transmission between PCM exchanges can also be effective.